1. Field of the Invention
The present invention relates to semiconductor devices, particularly to structures of semiconductor devices, and more particularly to post passivation structures for semiconductor devices and packaging processes for such.
2. Description of Related Art
Semiconductor wafers are processed to produce IC (integrated circuit) chip having ever-increasing device density and shrinking feature geometries. Multiple conductive and insulating layers are required to enable the interconnection and isolation of the large number of semiconductor devices in different layers (e.g., active and passive devices, such as TFT, CMOS, capacitors, inductors, resistors, etc). Such large scale integration results in increasing number of electrical connections between various layers and semiconductor devices. It also leads to an increasing number of leads to the resultant IC chip. These leads are exposed through a passivation layer of the IC chip, terminating in I/O pads that allow connections to external contact structures in a chip package.
Wafer-Level Packaging (WLP) refers to the technology of packaging an IC chip at wafer level, instead of the traditional process of assembling the package of each individual unit after wafer dicing. WLP allows for the integration of wafer fabrication, packaging, test, and burn-in at the wafer level, before being singulated by dicing for final assembly into a chip carrier package (e.g., a ball grid array (BGA) package). The advantages offered by WLP include smaller size (reduced footprint and thickness), lesser weight, relatively easier assembly process, lower overall production costs, and improvement in electrical performance. WLP therefore streamlines the manufacturing process undergone by a device from silicon start to customer shipment. While WLP is a high throughput and low cost approach to IC chip packaging, it however invites significant challenges in manufacturability and structural reliability.
WLP basically consists of extending the wafer fabrication processes to include device interconnection and device passivation processes. The first step to WLP is to enlarge the pad pitch of standard ICs by redistribution technology post passivation of the IC semiconductor structure. Low cost stencil printing of solder or placing preformed solder balls is then possible. Examples of redistribution technology are disclosed, for example, in U.S. Pat. No. 6,642,136; U.S. Pat. No. 6,784,087; and U.S. Pat. No. 6,818,545, commonly assigned to the assignee of the present invention. As disclosed in these patents, a redistribution layer (RDL) contacts the I/O pad of the semiconductor structure. The RDL is supported on a layer of polymer or elastomer deposited over a passivation layer. A contact post is formed on the RDL, using a photo-masking process. The resultant contact post is freestanding, unsupported on its lateral sides. The resultant structure can be further assembled into a chip carrier package using flip chip assembly technique. While the post passivation structures and related processes provide for IC packaging with improved pitch resolution, there is still a limitation to meeting the increasing demand for finer pitch resolution in view of the ever increasing scale of integration in ICs. There is also potential risk for stress-induced failures, as noted below.
U.S. Pat. No. 6,103,552 discloses another WLP process including a post passivation RDL. The RDL is supported on a layer of polymeric material that is deposited on the passivation layer of the semiconductor structure. Another polymeric layer is deposited over the RDL, and etched or drilled to provide a via for over-filling with a metal to form an interconnect (i.e., a conducting post) that extends above and beyond the opening of the via. The top polymeric layer and the bottom polymeric layer are separated by a layer of chrome-copper, and therefore do not touch between the RDL structures. A solder bump attached to the protruding end of the post is formed by electroless plating, screen or stencil printing. Because the post extends beyond the surface of the polymeric layer, and the top surface of the structure is otherwise not smooth, high-resolution lithography cannot be achieved to form the vias for the conductive posts and to plate the solder bumps. Consequently, the pitch of the contacts for the IC package would be limited. This limitation would be more pronounced with an increase in thickness of the polymeric layer, which otherwise may be desirable to provide better stress relief, as discussed below. Further, as noted, the bottom polymeric layer is separate from the top polymeric layer, therefore the bottom polymeric layer alone does not provide good stress relief. If the bottom polymeric layer is made thin to reduce lateral RDL displacements, stress relief would be poor, leading to issues further discussed below.
One of the challenges to structural reliability includes providing adequate stress relief in the resultant WLP processed multilayered structure, including the semiconductor IC die and the additional post passivation structure. For example, the thin film bonded on the passivation layer is subject to biaxial stress that is thermally induced. Equation (1) represents a theoretical mathematical modeling of the biaxial thermal stress in the post passivation thin film in relationship to various physical parameters of the bonded structure on a silicon (Si) substrate:
                              σ          ppt                =                              1                          6              ⁢              R                                ⁢                                          ⁢                                                    Y                s                            ⁢                                                          ⁢                              x                Si                2                                                                    (                                  1                  -                                      v                    Si                                                  )                            ⁢                                                          ⁢                              x                ppt                                                                        Equation        ⁢                                  ⁢                  (          1          )                    where:
σppt=σx=σy; biaxial stress in the post passivation thin film;
R=radius of curvature of the Si substrate caused by thermal stress;
YS=Young's modulus of Si substrate;
vsi=Poisson's ratio of Si substrate;
xSi=thickness of Si substrate; and
xppt=thickness of the post-passivation thin film.
Based on the above formula, there are two ways to lowering the biaxial stress σppt (in addition to increasing vsi): (a) lower xSi, which means making the Si substrate thinner; or (b) increase xppt, which means increasing the thickness of the post-passivation thin film structure.
FIG. 1 schematically shows a prior art post passivation structure 10, including an RDL 12 and a stress-relieving polymer (or stress buffer) layer 14, formed over a passivation layer 16 at the top layer of the semiconductor IC chip 18. The polymer layer 14 is made of, for example, an elastomer, epoxy, low-K dielectric material, or other polymer. Elastomer is used mainly for providing sufficient mechanical flexibility for the bonded structure. As can also be deduced from Equation (1) above, when a polymer layer is deposited over an IC chip 18, the stress generated by the chip and the structure bonded thereto can be absorbed or buffered to reduce local damage to the chip; this in turn enhances the reliability of the structure 10, especially the delicate circuits in the IC chip. According to the relationship set forth in Equation (1), the performance of this buffering effect is increased as the thickness of the polymer layer increases.
There is a generic problem associated with using a thick polymer layer. The RDL 12 shown in FIG. 1 is typically made of copper; it is intended to connect IC I/O pads 20 on the IC chip 18 to external circuitry. When deposited with solder bumps and/or provided with copper conductive post atop at pads 22, the RDL 12 can be bonded to the next level packaging structure firmly (e.g., a chip carrier). The RDL 12 escalates from a lower plane (i.e., the plane with the IC I/O pads 20) to a higher one (the top of the polymer) via a sloping ramp 22 defined by the polymer layer 14. The slope in the ramp 22 is desired for metal step coverage on the sidewall of the thick opening in the polymer layer 14. In practice, the slope of the ramp 22 could vary for each opening in the polymer layer 14, depending on the actual process conditions and inherent physical properties and characteristics of the polymer (e.g., wetting angle, which has to do with the surface energy of the materials). For example, in many cases the slope of the ramp 22 in the polymer layer 14 on the IC passivation layer 16 can be as low as about 45°. Consequently, the RDL 12 must necessarily translate by a significant amount of lateral displacement to extend from the IC I/O pad 20 to the top of the thick layer of polymer 14. Consequently, this lateral displacement necessitates the allowance of a significant amount of tolerance in the layout of the RDL 12. As a result of the tolerance allowance necessary to accommodate the varying slopes of ramps for different openings in the polymer layer 14 and the varying lateral displacements of RDLs, the pitch between adjacent contact structures (e.g., defined by solder bumps and/or copper posts) on the RDLs is limited, and the distances between the contact structures and the openings in the passivation layer are increased. This results in a post passivation structure that does not have fine pitch structures for the next level of packing structure. On the other hand, if a thick layer of polymer is not used, stress buffering would not be sufficient, leading to possible stress induced failure of the delicate circuits in the IC chip. Further, there would be insufficient lateral support to tall conductive posts, resulting in limited pitch of the I/O structures. It is desirable to have tall conductive posts, as they provide sufficient distance to reduce capacitance coupling between the I/O pads 22 and the electrical circuits in the IC chip 18.
The issues noted above collectively placed a limitation on reducing the pitch of the contact structures achievable on the post passivation structures, and thus also a limitation on increasing the scale of integration of ICs.
It is desirable to provide a WLP structure, and a process relating to same, that allows for both improved stress relief and fine pitch contact structures.